TSL2014 896 1 linear sensor array taos040 august 2002 1 the lumenology company copyright 2002, taos inc. www.taosinc.com 896 1 sensor-element organization 200 dots-per-inch (dpi) sensor pitch high linearity and uniformity wide dynamic rang e... 2000:1 (66 db) output referenced to ground low image lag . . . 0.5% typ operation to 5 mhz single 5-v supply 112 mm active length description the TSL2014 linear sensor array consists of two sections of 448 photodiodes and associated charge amplifier circuitry that can be connected to form a contiguous 896 1 array. the pixels measure 120 m m (h) by 70 m m (w) with 125- m m center-to-center spacing and 55- m m spacing between pixels. operation is simplified by internal control logic that requires only a serial-input (si) signal and a clock. the TSL2014 is intended for use in a wide variety of applications including mark detection and code reading, optical character recognition (ocr) and contact i maging, edge detection and positioning as well as optical linear and rotary encoding. functional block diagram (each section) si1 (si2) clk 448-bit shift register q448 (896) switch control logic integrator reset _ + pixel 1 (449) pixel 2 (450) pixel 448 (896) pixel 3 (451) sample/ output analog bus output amplifier gain trim q3 q2 q1 v dd r l external load ao1 (ao2) so1 (so2) texas advanced optoelectronic solutions inc. 800 jupiter road, suite 205 plano, tx 75074 (972) 673-0759 v dd 1 si1 2 ao1 3 so1 4 si2 5 clk 6 gnd 7 ao2 8 so2 9 v dd 10 package (top view)
TSL2014 896 1 linear sensor array taos040 august 2002 2 copyright 2002, taos inc. the lumenology company www.taosinc.com terminal functions terminal i/o description name no. i/o description ao1 3 o analog output of section 1. ao2 8 o analog output of section 2. clk 6 i clock. the clock controls the charge transfer, pixel output and reset. gnd 7 ground (substrate). all voltages are referenced to gnd. si1 2 i serial input (section 1). si1 defines the start of the data-out sequence. si2 5 i serial input (section 2). si2 defines the start of the data-out sequence. so1 4 o serial output (section 1). so1 signals the end of the data out sequence and provides a signal to drive the input of section 2 (si2) in serial mode. so2 9 o serial output (section 2). so2 signals the end of the data out sequence and provides a signal to drive the input of another device for cascading. vdd 1, 10 supply voltage. supply voltage for both analog and digital circuits. detailed description the sensor consists of 896 photodiodes arranged in a linear array. light energy impinging on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. during the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. the amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. the integration time is the interval between two consecutive output periods. the output and reset of the integrators is controlled by two 448-bit shift registers and reset logic. a 448-pixel output cycle is initiated by clocking in a logic 1 into the si input of a section for one positive going clock edge (see figures1 and 2) 2 . the two 448-pixel sections may be operated independently using a single clock input or connected in series to form a 896-pixel array. each section has an independent output (ao), which may be connected together for the 896-pixel function. when operating in the 896-pixel mode, as the si pulse is clocked through the 896-bit shift register, the charge on the sampling capacitor of each pixel is sequentially connected to a charge-coupled output amplifier that generates a voltage output, ao. when the bit position goes low, the pixel integrator is reset. on the 897 th clock rising edge, the si pulse is clocked out of the shift register (s2) and the output assumes a high-impedance state. note that this 897 th clock pulse is required to terminate the output of the 896 th pixel and return the internal logic to a known state. a subsequent si pulse can be presented as early as the 898 th clock pulse, thereby initiating another pixel output cycle. the voltage developed at analog output (ao) is given by: v out = v drk + (r e ) (e e ) (t int ) where: v out is the analog output voltage for white condition v drk is the analog output voltage for dark condition r e is the device responsivity for a given wavelength of light given in v/( m j/cm 2 ) e e is the incident irradiance in m w/cm 2 t int is integration time in seconds ao is driven by a source follower that requires an external pulldown resistor (330- w typical). the output is nominally 0 v for no light input, 2 v for normal white-level, and 3.4 v for saturation light level. when the device is not in the output phase, ao is in a high impedance state. a 0.1 m f bypass capacitor should be connected between v dd and ground as close as possible to the device. 2 for proper operation, after meeting the minimum hold time condition, si must go low before the next rising edge of the clock.
TSL2014 896 1 linear sensor array taos040 august 2002 3 the lumenology company copyright 2002, taos inc. www.taosinc.com absolute maximum ratings 2 supply voltage range, v dd 0.3 v to 6 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage range, v i 0.3 v to v dd + 0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input clamp current, i ik (v i < 0 or v i > v dd ) 20 ma to 20 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output clamp current, i ok (v o < 0 or v o > v dd ) 25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range applied to any output in the high impedance or power-off state, v o 0.3 v to v dd + 0.3v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous output current, i o (v o = 0 to v dd ) 25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous current through v dd or gnd 150 ma to 150 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . analog output current range, i o 25 ma to 25 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a 25 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range, t stg 25 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature on solder pads for 10 seconds 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . esd tolerance, human body model 2000 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 stresses beyond those listed under aabsolute maximum ratingso may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under arecommended operating conditi onso is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions (see figure 1 and figure 2) min nom max unit supply voltage, v dd 4.5 5 5.5 v input voltage, v i 0 v dd v high-level input voltage, v ih 2 v dd v low-level input voltage, v il 0 0.8 v wavelength of light source, l 400 1000 nm clock frequency, f clock 5 5000 khz sensor integration time, serial t int 0.1792 100 ms sensor integration time, parallel t int 0.090 100 ms operating free-air temperature, t a 0 70 c load resistance, r l 300 4700 w load capacitance, c l 330 pf
TSL2014 896 1 linear sensor array taos040 august 2002 4 copyright 2002, taos inc. the lumenology company www.taosinc.com electrical characteristics at f clock = 200 khz, v dd = 5 v, t a = 25 c, l p = 640 nm, t int = 5 ms, r l = 330 w , e e = 18 m w/cm 2 (unless otherwise noted) parameter test conditions min typ max unit v out analog output voltage (white, average over 896 pixels) see note 1 1.6 2 2.4 v v drk analog output voltage (dark, average over 896 pixels) 0 0.05 0.15 v prnu pixel response nonuniformity see notes 2 & 3 7% 20% nonlinearity of analog output voltage see note 3 0.4% fs output noise voltage see note 4 1 mvrms r e responsivity 16 22 28 v/ (m j/cm 2 ) se saturation exposure see note 5 155 nj/cm 2 v sat analog output saturation voltage 2.5 3.4 v dsnu dark signal nonuniformity all pixels see note 6 25 120 mv il image lag see note 7 0.5% i dd supply current, output idle 53 80 ma i ih high-level input current v i = v dd 10 m a i il low-level input current v i = 0 10 m a v o high level out p ut voltage so1 and so2 i o = 50 m a 4.5 4.95 v v oh high-level output voltage, so1 and so2 i o = 4 ma 4.6 v v o low level out p ut voltage so1 and so2 i o = 50 m a 0.01 0.1 v v ol low-level output voltage, so1 and so2 i o = 4 ma 0.4 v c i(si) input capacitance, si 35 pf c i(clk) input capacitance, clk 70 pf notes: 1. the array is uniformly illuminated with a diffused led source having a peak wavelength of 640 nm. 2. prnu is the maximum difference between the voltage from any single pixel and the average output voltage from all pixels of th e device under test when the array is uniformly illuminated at the white irradiance level. prnu includes dsnu. 3. nonlinearity is defined as the maximum deviation from a best-fit straight line over the dark-to-white irradiance levels, as a percent of analog output voltage (white). 4. rms noise is the standard deviation of a single-pixel output under constant illumination as observed over a 5-second period. 5. minimum saturation exposure is calculated using the minimum v sat , the maximum v drk , and the maximum r e . 6. dsnu is the difference between the maximum and minimum output voltage in the absence of illumination. 7. image lag is a residual signal left in a pixel from a previous exposure. it is defined as a percent of white-level signal rem aining after a pixel is exposed to a white condition followed by a dark condition: il v out (il) v drk v out (white) v drk 100 timing requirements (see figure 1 and figure 2) min nom max unit t su(si) setup time, serial input (see note 8) 20 ns t h(si) hold time, serial input (see note 8 and note 9) 0 ns t w pulse duration, clock high or low 50 ns t r , t f input transition (rise and fall) time 0 500 ns notes: 8. input pulses have the following characteristics: t r = 6 ns, t f = 6 ns. 9. si must go low before the rising edge of the next clock pulse.
TSL2014 896 1 linear sensor array taos040 august 2002 5 the lumenology company copyright 2002, taos inc. www.taosinc.com dynamic characteristics over recommended ranges of supply voltage and operating free-air temperature (see figure 2) parameter test conditions min typ max unit t s analog output settling time to 1% r l = 330 w c l = 10 pf 185 ns t pd propagation delay time, so1 and so2 50 ns typical characteristics ???????????????????? ???????????????????? ???????????????????? ??????? ??????? ??????? 449 clock cycles clk si ao hi-z hi-z figure 1. timing waveforms (each section) ao1 (a02) si1 (si2) clk pixel 448 (896) t s 0 v 0 v 5 v 2.5 v t h(si) 5 v t su(si) t w 1 (449) 2 (450) 448 (896) 449 (897) t s pixel 1 (449) 2.5 v 2.5 v 2.5 v 2.5 v t pd(so) t pd(so) so1 (so2) figure 2. operational waveforms (each section)
TSL2014 896 1 linear sensor array taos040 august 2002 6 copyright 2002, taos inc. the lumenology company www.taosinc.com typical characteristics 0.4 0 300 500 700 900 0.6 0.8 photodiode spectral responsivity 0.2 l wavelength nm normalized responsivity t a = 25 c 1 1100 400 600 800 1000 figure 3 figure 4 analog output settling time vs load capacitance and resistance r l load resistance w 200 0 0 400 800 1200 300 400 100 v dd = 5 v v out = 1 v 500 200 600 1000 t s e settling time to 1% e ns 600 100 pf 470 pf 220 pf 10 pf application information v dd 1 si1 2 ao1 3 so1 4 si2 5 clk 6 gnd 7 ao2 8 so2 9 v dd 10 si input ao 1/ao 2 clock input TSL2014 serial si input ao 1 clock input TSL2014 parallel ao 2 v dd 1 si1 2 ao1 3 so1 4 si2 5 clk 6 gnd 7 ao2 8 so2 9 v dd 10 r l 330 r l 330 r l 330 figure 5. connection diagrams
TSL2014 896 1 linear sensor array taos040 august 2002 7 the lumenology company copyright 2002, taos inc. www.taosinc.com mechanical information 4.32 3.80 4.32 3.80 16.95 16.45 120.14 119.89 2.54 49.02 48.77 3.05 9.525 9.271 pixel 896 pixel 1 pin 10 pin 1 c l a a section aa scale 6 : 1 1 1.22 0.96 0.69 bonded array die bypass capacitor 3.30 3.05 10 0.385 0.315 3 1.43 1.17 cover glass notes: a. all linear dimensions are in millimeters. b. cover glass index of refraction is 1.52. c. this drawing is subject to change without notice. figure 6. TSL2014 mechanical specifications
TSL2014 896 1 linear sensor array taos040 august 2002 8 copyright 2002, taos inc. the lumenology company www.taosinc.com production data e information in this document is current at publication date. products conform to specifications in accordance with the terms of texas advanced optoelectronic solutions, inc. standard warranty. production processing does not necessarily include testing of all parameters. notice texas advanced optoelectronic solutions, inc. (t aos) reserves the right to make changes to the products contained in this document to improve performance or for any other purpose, or to discontinue them without notice. customers are advised to contact taos to obtain the latest product information before placing orders or designing taos products into systems. taos assumes no responsibility for the use of any products or circuits described in this document or customer product design, conveys no license, either expressed or implied, under any patent or other right, and makes no representation that the circuits are free of patent infringement. taos further makes no claim as to the suitability of its products for any particu lar purpose, nor does taos assume any liability arising out of the use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. texas advanced optoelectronic solutions, inc. products are not designed or intended for use in critical applications in which the failure or malfunction of the taos product may result in personal injury or death. use of taos products in life support systems is expressly unauthorized and any such use by a customer is completely at the customer's risk. lumenology is a registered trademark, and taos, the taos logo, and texas advanced optoelectronic solutions are trademarks of texas advanced optoelectronic solutions incorporated.
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